8-10A1 D
In the circuit shown in Fig. 8A4, U5 pins 1 and 4 are high and both are in the reset state. Assume one clock cycle occurs of Clk A followed by one cycle of Clk B. What are the output states of the two D-type flip flops?
A. Pin 5 low, Pin 9 low.
B. Pin 5 high, Pin 9 low.
C. Pin 5 low, Pin 9 high.
D. Pin 5 high, Pin 9 high.
